Nonvolatile memory and method for driving nonvolatile memory

ABSTRACT

A memory cell includes a MOS transistor having a source region, a drain region and a gate electrode, a ferroelectric film formed on the source region of the MOS transistor via an insulating film and an electrode formed on the ferroelectric film. The memory cell can be composed of a smaller number of elements while preventing data corruption and disturbance at the time of readout.

TECHNICAL FIELD

The present invention relates to a nonvolatile memory device and amethod for driving the same.

BACKGROUND ART

As one example of a nonvolatile memory device, those which use a fieldeffect transistor including a ferroelectric film in a gate (hereinafter,referred to as a “ferroelectric FET”) have been proposed. Theferroelectric FET has a ferroelectric film and a gate electrode on aswitching MOS-FET to form a nonvolatile memory device. As shown in FIG.6, the ferroelectric FET is configured by successively forming aninsulating film 13, a ferroelectric film 12 and a gate electrode 14 on asubstrate 8 where a source region 5 and a drain region 6 are formed.

In the above-mentioned configuration, the ferroelectric film 12 may bepolarized upward or downward. Assuming that the threshold voltage of theMOS-FET can be set at either of two different values corresponding tothe two polarization states, the set state can be held (stored) as longas the polarization state of the ferroelectric film 12 is held. As shownin FIG. 7, a word line W is connected to the gate of the transistor, abit line B to the drain region, and a source region line S to the sourceregion, thereby configuring a memory cell as an element at eachintersection of a matrix array.

The matrix array of the conventional nonvolatile memory device composedof the above-described memory cells has a configuration as shown in FIG.8, for example. In FIG. 8, M11, M12, M21 and M22 denote a transistor,respectively, which constitutes each memory cell, C11, C12, C21 and C22at each intersection of the matrix array. W1 denotes a word lineconnected to each gate of the transistors M11 and M12. W2 denotes a wordline connected to each gate of the transistors M21 and M22. S1 denotes asource region line connected to each source region of the transistorsM11 and M12. S2 denotes a source region line connected to each sourceregion of the transistors M21 and M22. B1 denotes the bit line connectedto each drain region of the transistors M11 and M21. B2 denotes a bitline connected to each drain region of the transistors M12 and M22.

The logic state of a memory cell is distinguished depending upon whetherthe transistor M11, M12, M21 or M22 of the selected memory cell is in anON or OFF state. Whether the transistor is in an ON or OFF state isdetermined depending upon whether a channel under the gate of thetransistor is conducting or not. A gate voltage, by which the channel ofthe transistor is conducted when applied to the gate of the transistor,that is, a threshold voltage, can be separated corresponding to the twopolarization states of the ferroelectric film. For instance, a gate anda channel can be configured so that the transistor is turned ON in onepolarization state, while the transistor is turned OFF in the otherpolarization state when a voltage is applied to the gate. Then, a logicof the transistor in the ON state is defined as “1”, and that in the OFFstate is defined as “0”, for example.

In order to find a logic held in, for example, the memory cell C11 inFIG. 8, on the basis of the above definition, the following operationshould be conducted. First, the bit line B1 is discharged to a lowvoltage. Then, the voltage of the source region line S1 is increased toa readout voltage. Thereafter, the intermediate voltage between theabove-described two threshold voltages is applied to the word line W1.When the ferroelectric film of the transistor M11 is in a low thresholdvoltage state (i.e., “1”), the transistor M11 is turned ON.Consequently, an electric current flows from the source region line S1to the bit line B1, whereby the bit line B1 is charged, and the voltagethereof is increased. On the other hand, when the ferroelectric film ofthe transistor M11 is in a high threshold voltage state, (i.e., “0”),the transistor M11 is turned OFF. Consequently, the bit line B1 is notcharged, and the voltage thereof remains low. Therefore, the logic stateheld in the desired memory cell can be distinguished depending upon thehigh or low state of the voltage of the bit line B1.

However, in the case where a voltage is applied to the word line W1 orW2 every time data are read out, the ferroelectric film of the gate inthe state “0” is applied with a voltage in a direction graduallyapproaching the state “1”, even when the value of the voltage isintermediate between the two threshold voltages corresponding to theabove-mentioned polarization states of the ferroelectric film. As aresult, all the ferroelectric films connected to the word line, to whichthe readout voltage is applied and which are in the state “0”, graduallyapproach the state “1”, every time data is read out. Accordingly, itgradually becomes difficult to discriminate the state between “0” and“1”, that is, a so-called disturbance occurs.

In order to avoid such a problem, the transistor may be designed to beset in either an enhancement state or a depletion state in accordancewith the polarization state of the ferroelectric film. When therespective states are brought into correspondence with the two logicvalues, it is not required to apply a voltage to the word line at thetime of readout.

However, the depletion-type transistor is a normally-on type, that is,in the state “1”, even when the gate voltage is zero. Therefore, thefollowing problem might arise.

When the logic held in a non-selected memory cell is “1”, a current pathfrom the bit line to the source line is formed via the non-selectedmemory cell. Then, the potential of the bit line might be varied inaccordance with the state of the non-selected memory cell. To avoidthis, a transistor for connecting only the transistor of the selectedmemory cell to the bit line is required to be added to the memory cell.

Further, in order to selectively write data only onto the transistor ofa randomly selected memory cell, the substrate of the ferroelectric FETof each memory cell should be separated electrically by a well at leastfrom the substrate of the ferroelectric FET of the memory cell connectedto the adjacent word line or bit line. To solve this problem, it isnecessary to add a selecting transistor to the gate of the transistor.

When the ferroelectric FETs as memory cells are arranged in a matrix inaccordance with the above-described measures, a configuration as shownin FIG. 9 is obtained. According to this configuration, it is requiredto provide selecting transistors TP and TB between a ferroelectric FET(M) and a word line WP, and between the ferroelectric FET (M) and a bitline B, respectively. Therefore, there arises the disadvantage that thememory cell is increased in size by several times that of a memory cellhaving one transistor and one capacitor (1C-1Tr memory cell).

DISCLOSURE OF THE INVENTION

Therefore, with the foregoing in mind, it is an object of the presentinvention to provide a nonvolatile memory device that prevents datacorruption and disturbance when the data is read out from a memory cell,and in which a memory cell is composed of a smaller number of elements,and a method for driving the same.

To solve the above-described problems, a nonvolatile memory device ofthe present invention includes a MOS transistor having a source region,a drain region and a gate electrode, a ferroelectric film formed on thesource region via an insulating film, and an electrode formed on theferroelectric film. According to this configuration, the polarizationstate of the ferroelectric film formed on the source region affects thequantity of flow of electrons injected to a channel in a direction fromthe source region to the drain region of the MOS transistor, whereby thelogic state held in the memory cell can be distinguished. In thisconfiguration, since a voltage applied to the gate electrode at the timeof readout has no influence on the ferroelectric film, the datacorruption and disturbance at the time of readout of data from thememory cell can be avoided. Further, a nonvolatile memory deviceconstituted by a memory cell composed of a smaller number of elementscan be obtained.

In the above-configured nonvolatile memory device, it is preferable thatthe insulating film composed of a plurality of layers is formed betweenthe source region of the MOS transistor and the ferroelectric film. Thisconfiguration can prevent a direct contact between the surface of thechannel and the ferroelectric film and inhibit oxidation at theinterface of the source region during growth of crystal of theferroelectric film.

Further, the nonvolatile memory device of the present invention can beconfigured so as to have memory cells arranged in a matrix, each unit ofthe memory cell including a MOS transistor having a source region, adrain region and a gate electrode, a ferroelectric film formed on thesource region via an insulating film, and an electrode formed on theferroelectric film. This configuration allows a memory unit (memorycell) to be randomly selected and data to be read from or written to thememory cell without the non-selected memory being read out irrespectiveof the enhancement-type or the depletion-type transistor.

Further, a method for driving a nonvolatile memory device of the presentinvention is the one for driving a nonvolatile memory device including aMOS transistor having a source region, a drain region and a gateelectrode, a ferroelectric film formed on the source region via aninsulating film and an electrode formed on the ferroelectric film.According to this method, the polarization state of the ferroelectricfilm can be detected based on the quantity of flow of electrons injectedfrom the source region to the drain region via the channel under thegate electrode, under the application of a bias voltage, by which thedrain region becomes positive, to the source region. This method allowsthe quantity of flow of electrons injected from the source region to thedrain region of the MOS transistor to be reflected by the polarizationstate of the ferroelectric film formed on the source region. Therefore,the logic state held in the memory cell can be distinguished.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional view of a ferroelectric FET constituting anonvolatile memory device according to an embodiment of the presentinvention.

FIG. 2 is a cross-sectional view illustrating an operation of theferroelectric FET in FIG. 1.

FIGS. 3A and 3B are views showing the energy band in a cross section ofthe ferroelectric FET taken along a line A—A in FIG. 2.

FIG. 4 is a view showing that two potential distributions areoverlapped: the distribution in an area crossing from the ferroelectricfilm on the source region to the substrate and that in an area crossingfrom the gate to the substrate in the ferroelectric FET in FIG. 1.

FIG. 5 is a circuit diagram showing a memory cell using theferroelectric FET in FIG. 1.

FIG. 6 is a cross-sectional view of a conventional ferroelectric FET.

FIG. 7 is a circuit diagram showing a memory cell using theferroelectric FET in FIG. 6.

FIG. 8 is a circuit diagram showing a conventional nonvolatile memorydevice in which the memory cells in FIG. 7 are arranged in a matrixarray.

FIG. 9 is a circuit diagram showing a configuration in which a selectingtransistor is added to the ferroelectric FET in the memory cell in FIG.7.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the nonvolatile memory device according to an embodiment ofthe present invention will be described with reference to FIGS. 1 to 5.

FIG. 1 shows a ferroelectric FET constituting the nonvolatile memorydevice according to an embodiment of the present invention. A switchingMOS-FET transistor is formed by providing an insulating film 3 on asilicon substrate 8 where a source region 5 and a drain region 6 areformed, and further providing a gate electrode 4. A ferroelectric film 2and an electrode 1 are formed on the insulating film 3 covering the gateelectrode 4 so as to be superimposed on the source region 5 and aportion of the gate electrode 4.

The insulating film 3 is composed of an oxide film or nitride film madeof silicon oxide, silicon nitride or silicon oxynitride; a metal oxidewith a high dielectric constant; or the like. Further, the insulatingfilm 3 may be composed of plural layers of different materials. The gateelectrode 4 is composed of metal such as doped polysilicon, aluminum,copper or the like. The ferroelectric film 2 is composed of a metaloxide such as bismuth-strontium-tantalum oxide or the like.

In the following description, an example will be described in which thesubstrate 8 is made of P-type silicon, and the source region 5 and thedrain region 6 are doped to be an N-type. In this configuration, theferroelectric film 2 is polarized upward or downward in advance by usinga circuit connected between the electrode 1 and the source region 5.Thereafter, as shown in FIG. 2, the electrode 1, the source region 5 andthe substrate 8 are grounded. In this state, a cross section taken alonga line A—A is in a thermal equilibrium state irrespective of whether theferroelectric film 2 is polarized upward or downward. FIGS. 3A and 3Bshow the energy band in the cross section taken along the line A—A inthis state. Reference numerals in FIGS. 3A and 3B correspond to thesubstrate 8, the source region 5, the insulating film 3, theferroelectric film 2 and the electrode 1 that constitute theferroelectric FET in FIG. 2, respectively.

The direction of an arrow in FIGS. 3A and 3B indicates the direction ofthe polarization of the ferroelectric film 2. FIG. 3A corresponds to thecase where the polarization is directed upward. FIG. 3B corresponds tothe case where the polarization is directed downward. According to thecomparison between these figures, it can be found that the potential atthe interface between the insulating film 3 and the source region 5 isvaried depending upon the direction of the polarization. Morespecifically, when the polarization is directed upward, the potential ofthe source region 5 under the insulating film 3 is elevated by apolarization charge. On the other hand, when the polarization isdirected downward, the potential of the source region 5 under theinsulating film 3 remains flat.

FIG. 4 shows that two potential distributions corresponding to twopolarization states are overlapped with each other: the distribution inthe cross section of the source region 5 taken along the line A—A andthat in the cross section from the gate electrode 4 of the MOStransistor to a channel 7 taken along a line B—B in FIG. 2. Morespecifically, FIG. 4 is a view showing the potentials of the gateelectrode 4, the insulating film 3, and the source region 5 or thesubstrate 8. The potential distribution in the cross section taken alongthe line A—A is represented by a solid line, and that taken along theline B—B is represented by dashed lines. Two potential distributionsrepresented by the dashed lines correspond to the case where thepotential of the gate electrode 4 is Vth and to the case where thepotential of the gate electrode 4 is Vth*, respectively.

In the cross section taken along the line A—A, the potential of thesource region 5 in the vicinity of the interface between the insulatingfilm 3 and the source region 5 is elevated high when the polarization isdirected upward (i.e., in the case of FIG. 3A). On the other hand, thepotential remains flat when the polarization is directed downward,(i.e., in the case of FIG. 3B). Therefore, the case of FIG. 3A isdefined as an “OFF state” (i.e., “0”), while the case of FIG. 3B isdefined as an “ON” state (i.e., “1”).

In order for electrons to flow from the source region 5 to the channel7, a bias is applied between the source region 5 and the drain region 6so that the drain region 6 becomes positive, to increase the potentialof the gate electrode 4. In the case where the source region 5 is in anON state, when the potential of the gate electrode 4 increases to reachVth in FIG. 4, the potential of the source region 5 becomes equal tothat of the channel 7 under the gate. Then, electrons start to flow fromthe source region 5 to the channel 7. In the case where the sourceregion 5 is in an OFF state, the lowest portion of the potential of thesource region 5 is not matched with the potential of the channel 7 untilthe potential of the gate electrode 4 reaches Vth*. Accordingly, if thepotential of the gate electrode 4 is set in a range from Vth to Vth*,the direction of the polarization can be distinguished depending onwhether or not the electrons are injected from the source region 5 tothe channel 7.

As described above, there is a difference in the quantity of electronsflowing from the source region 5 to the channel 7 between an ON stateand an OFF state. Therefore, when the potential of the gate electrode 4is set in the range where the difference in the quantity of flow ofelectrons occurs and a bias voltage is applied to the source region 5 sothat the drain region 6 becomes positive, the difference appears in thequantity of electrons flowing from the source region 5 to the drainregion 6 via the channel 7 under the gate electrode 4. Thus, the logicstate held in the memory cell can be distinguished between “0” and “1”by detecting the polarization state of the ferroelectric film 2.

Further, since the ferroelectric film 2 is formed on the source region5, even when a voltage is applied to the gate electrode 4 of the MOStransistor to select a memory cell, the polarization state of theferroelectric film 2 is not influenced by the applied gate voltage.Thus, the occurrence of disturbance can be avoided.

In the embodiment of the present invention, the ferroelectric film 2 isformed on the source region 5 and a portion of the gate electrode 4.However, the ferroelectric film 2 may be formed only on the sourceregion 5, or only on a portion of the source region 5.

Since the insulating film 3 is provided between the source region 5 andthe ferroelectric film 2, when the ferroelectric film 2 is formed, theinterface of the source region 5 can be prevented from oxidation thatmight occur during the growth of crystal of the ferroelectric film.

The nonvolatile memory device of the embodiment of the present inventionis configured by arranging the memory cells as shown in FIG. 5, whichemploy the foregoing ferroelectric FET as a memory unit in a matrix.

The memory cell in FIG. 5 includes a first MOS transistor T1 and asecond MOS transistor T2. The first MOS transistor T1 is the foregoingferroelectric FET, that is, a MOS transistor composed of theferroelectric film formed on the source region. Reference numeral 20denotes a ferroelectric capacitor composed of the ferroelectric film.The gate of the first MOS transistor T1 is connected to a word line W,the drain region to a bit line B and the source region to a source lineS. The electrode 1 (see FIG. 1) of the ferroelectric capacitor 20 isconnected to a program line P via the second MOS transistor T2, and thegate of the second MOS transistor T2 to the bit line B.

As described above, the memory cell according to the present embodimenthas a reduced number of elements as compared with the prior art in FIG.9. More specifically, the ferroelectric FET (M) in FIG. 9 is required tobe provided with selecting transistors TB and TP. In contrast, accordingto the present embodiment, it is not required to add a transistorequivalent to the selecting transistor TB. Further, as described in thefollowing, the memory cell of the present invention can be operatedsimilarly to the memory cell of the prior art in FIG. 9.

Hereinafter, a method for driving the memory cell in FIG. 5 will bedescribed in the case where the memory cells are arranged in a matrix.Here, the first MOS transistor T1 in the memory cell corresponds to theenhancement type or depletion type.

At the time of readout of the memory cell in FIG. 5, first, all thelines are set at a low voltage (e.g., ground voltage). Then, a highvoltage between Vth and Vth* is applied to the word line. Subsequently,when the bit line B is set at a high voltage, an electric current doesnot flow to the source line S when the polarization is directed upward(OFF), while an electric current flows to the source line S when thepolarization is directed downward (ON).

In the case where a plurality of memory cells which perform the readoutoperation as described above are arranged in a matrix, if each of theword lines of the non-selected memory cells connected to the common bitline B is set at a low voltage, each of the MOS transistors of thenon-selected memory cells is in a high-impedance state. Therefore, thestate of only the selected memory cell can be detected by the potentialof the bit line B or that of the source line S. Further, even when theword line W is set at a high voltage at the time of readout, the voltageis not applied to the ferroelectric capacitor 20. Therefore, thepolarization state is not influenced.

Data can be erased from a desired memory cell (the source potential canbe turned OFF) as follows. The program line P is set at a low voltage,and the word line is retained at a low voltage. Under this condition,the bit line is set at a high voltage to turn on the second MOStransistor T2. Consequently, the ferroelectric capacitor 20 and theprogram line P are connected to each other electrically. Next, thesource line S is set at a high voltage. Thereby, a voltage equal to orhigher than that which reverses the polarization state of theferroelectric capacitor 20 is applied between the program line P and thesource line S.

Data can be written onto a desired memory cell (the source potential canbe turned ON) as follows. The word line W is set at a low voltage. Underthis condition, the bit line B is set at a high voltage to turn on thesecond MOS transistor T2. Consequently, the ferroelectric capacitor 20and the program line P are connected to each other electrically. Next,the source line S is set at a low voltage, and the program line P is setat a high voltage. Thereby, a voltage equal to or higher than that whichreverses the polarization state of the ferroelectric capacitor 20 isapplied between the program line P and the source line S.

As described above, in the case where the memory cell in FIG. 5 isarranged in a matrix, irrespective of whether the first MOS transistorT1 is of an enhancement type or a depletion type, a current path to thebit line B is not formed due to the non-selected memory cell. Therefore,data of only the selected memory cell can be obtained. Accordingly, thememory cell according to the embodiment of the present invention can becomposed of a smaller number of elements, while conducting an operationequal to that of the conventional memory cell composed of theferroelectric FET and the selecting transistors TP and TB.

Further, in the case where the memory cells according to the embodimentof the present invention are arranged in a matrix, a binary logic statecan be stored only in a selected memory cell corresponding to whether ornot the polarization is directed upward. The stored logic state can bedistinguished by being read out as long as the spontaneous polarizationis maintained.

INDUSTRIAL APPLICABILITY

According to the present invention, by using the property that thequantity of electrons flowing from a source region, on which aferroelectric film of a MOS transistor is superimposed, to a channeldepends upon the polarization state of a ferroelectric film, thepolarization state of the ferroelectric film, that is, data of a memorycell can be distinguished by a simple configuration and procedure.Further, since the polarization state is spontaneous, the polarizationstate can be held (stored), and the state can be reflected to a channelcurrent of a transistor (read out). Therefore, the effect of theferroelectric memory can be possessed.

The ferroelectric film is formed on the source region. Therefore, evenwhen a voltage is applied to the gate of the MOS transistor in order toselect a memory cell, the gate voltage does not affect the polarizationstate of the ferroelectric film, and hence, disturbance can be avoided.

In the nonvolatile memory device composed of the memory cells employingthe ferroelectric FET, the selecting transistor is not required to beadded to the word line and the bit line in each memory cell. Therefore,the memory cell is not increased in the size, and hence, the integrationcan be facilitated.

What is claimed is:
 1. A nonvolatile memory device comprising a memorycell including a MOS transistor having a source region, a drain regionand a gate electrode, a ferroelectric film formed on the source regionvia an insulating film, and an electrode formed on the ferroelectricfilm, wherein the insulating film is composed of a plurality of layers.2. A nonvolatile memory device comprising memory cells each including afirst transistor and a second transistor, the first transistor beingprovided with a ferroelectric film and an electrode on a source region,wherein a gate, a drain region and a source region of the firsttransistor are connected to a word line, a bit line and a source line,respectively; the electrode formed on the ferroelectric film isconnected to a program line via the second transistor; and a gate of thesecond transistor is connected to the bit line.
 3. The nonvolatilememory device according to claim 1 or 2, wherein the memory cells arearranged in a matrix.
 4. A method for driving a nonvolatile memorydevice comprising a MOS transistor having a source region, a drainregion and a gate electrode, a ferroelectric film formed on the sourceregion via an insulating film, and an electrode formed on theferroelectric film, the method comprising: applying a bias voltage tothe source region so that the drain region becomes positive; anddetecting a polarization state of the ferroelectric film depending upona quantity of flow of electrons injected from the source region to thedrain region via a channel under the gate electrode.